An electrically erasable and programmable nonvolatile read only memory is quite an important element in various LSI applied fields since stored information remains in each memory cell even if the memory is turned off.
There is described a so-called floating-gate nonvolatile memory and a nonvolatile memory using an insulating layer in S. Sze, “Physics of Semiconductor Devices, 2nd edition”, A Wiley-Interscience Publication (Non-Patent Document 1), pages 496-506. As disclosed in the Non-Patent Document 1, it is known that there is no need to separately form a conductive layer for accumulating charges in a nonvolatile memory in which charges are accumulated in a trap of an insulating layer or in an interface of a multilayer insulating layer, differently from a floating-gate nonvolatile memory in which charges are accumulated in a polycrystalline silicon layer. It is, therefore, possible to form memory cells with high consistency with CMOS-LSI process.
However, the nonvolatile semiconductor memory configured so that charges are accumulated in the insulating layer is required to include the insulating layer capable of maintaining sufficient charge holding characteristics even if injection and emission of charges are repeated. It is, therefore, difficult to realize such a nonvolatile semiconductor memory. There has been proposed, by contrast, a nonvolatile semiconductor memory that rewrites stored information by injecting charges having different signs in place of emitting charges. Operation performed by this nonvolatile semiconductor memory is described in “Symposium on VLSI Technology in 1997” (Non-Patent Document 2), pages 63-64. The nonvolatile semiconductor memory is characterized in that a polycrystalline silicon gate for causing each memory cell to operate and a gate for selecting one of the memory cells are formed separately. The same characteristic is also disclosed in U.S. Pat. No. 5,969,383 (Patent Document 1) and U.S. Pat. No. 6,477,084 (Patent Document 2).
A memory cell of the nonvolatile semiconductor memory disclosed in the Non-Patent Document 2 or the like is basically constituted by two transistors (a selective transistor and a memory transistor) each based on an n-channel MOSFET. The memory transistor is arranged next to the selective transistor to be connected to the selective transistor in a so-called ‘stacked in series’ manner. FIG. 35 is an equivalent circuit to the memory cell. FIG. 36 is a schematic of an example of a memory array constituted by such memory cells. Gates (a selective gate and a memory gate) of the selective transistor and the memory transistor constitute word lines SGL and MGL, and diffused layers thereof constitute a bit line BL and a source line SL, respectively.
In the memory cell shown in FIG. 35, a gate insulating layer of the memory gate is configured to have a so-called MONOS (metal-oxide-nitride-oxide-semiconductor) structure in which a silicon nitride layer serving as a charge trapped layer is held between two silicon dioxide layers. A gate insulating layer of the selective gate is constituted by a silicon dioxide layer. The selective gate-side diffused layer is formed by implantation of impurity ions with the selective gate used as a mask, and the memory gate-side diffused layer is formed by implantation of impurity ions with the memory gate used as a mask. Biases applied to these nodes are Vmg, Vcg, Vs, Vd, and Vbb, respectively (see FIG. 35).
Basic operations performed by the memory cell are four operations, i.e., (1) write, (2) erasing, (3) holding, and (4) read operations. It is to be noted that these four operations are denoted by typical notations and that the write and erasing operations are sometimes denoted differently. Furthermore, typical operations will be described; however, various other operations can be considered. Although the memory cell constituted by the n-channel MOSFETs will be described herein, a memory cell constituted by p-channel MOSFETs are identical to the former memory cell in principle.
FIG. 37 is a schematic for typically explaining the write operation performed by the memory cell, and FIG. 38 is a schematic for typically explaining the erasing operation performed by the memory cell. In FIGS. 37 and 38, reference symbol 50 denotes a semiconductor substrate (hereinafter, simply “substrate”) made of monocrystalline silicon, 51 denotes a selective gate, 52 denotes a memory gate, 53 denotes a gate insulating layer, 54 denotes an ONO layer, 55 denotes a selective gate-side diffused layer, and 56 denotes a memory gate-side diffused layer.
(1) In a write operation, a positive potential is applied to the diffused layer 56 on the memory gate 52 side, and the same ground potential as that applied to the substrate 50 is applied to the diffused layer 55 on the selective gate 51 side. By applying a gate overdrive voltage higher than that applied to the substrate 50 to the memory gate 52, a channel under the memory gate 52 is turned into an ON-state. By setting a potential of the selective gate 51 to a value higher than a threshold voltage by 0.1V to 0.2V, a channel under the selective gate 51 is turned into an ON-state. At this time, a highest electric field is generated near a boundary between the two gates 51 and 52, so that many hot electrons are generated and injected into the memory gate 52. A state of generating carriers by electric field acceleration and impact ionization is denoted by symbol A. An electron is denoted by a white circle and a hole is denoted by a hatched circle.
This phenomenon is known and referred to as “source side injection or SSI”, which is described in A. T. Wu et al., “IEEE International Electron Device Meeting”, Technical Digest, pages 584-587, 1986 (Non-Patent Document 3). In the Non-Patent Document 3, a floating-gate memory cell has been described. However, a memory cell in which an insulating layer is used as charge trapped layer is identical to the floating-gate memory cell in injection mechanism.
The hot electron injection by the above-stated method is characterized in that the hot electron injection concentrates on a selective gate 51-side end of the memory gate 52 because of concentration of the electric field near the boundary between the selective gate 51 and the memory gate 52. Furthermore, while in the floating gate-type memory cell, the charge trapped layer is constituted by a conductive layer, in an insulating layer-type memory cell, charges are accumulated in the insulating layer (ONO layer 54). Therefore, electrons are held in an extremely narrow region in the insulating layer-type memory cell.
(2) In an erasing operation, a negative potential is applied to the memory gate 52 and the positive potential is applied to the diffused layer 56 on the memory gate 52 side so as to cause strong inversion on an end of the diffused layer 56 on which the memory gate 52 overlaps with the diffused layer 56. An interband tunnel phenomenon is thereby generated and holes are generated (denoted by symbol B). The interband tunnel effect is disclosed in, for example, T. Y. Chan et al., “IEEE International Electron Device Meeting”, Technical Digest, pages 718-721, 1987 (Non-Patent Document 4).
In this memory cell, the generated holes are accelerated in channel direction, attracted by a bias applied to the memory gate 52, and injected into the ONO layer 54, whereby the erasing operation is performed. A state of generating a secondary electron-hole pair resulting from the generated hole is denoted by symbol C. The carries are also injected into the ONO layer 54. Namely, a threshold voltage of the memory gate 52 that has risen by electron charges can be reduced by charges of the injected holes.
(3) In a holding operation, the charges are held as the charges of the carriers injected into the ONO layer 54. Since movement of the carriers in the ONO layer 54 is quite small and slow, the charges can be satisfactorily held even if a voltage is not applied to the memory gate 52.
(4) In a read operation, by applying a positive potential to the selective gate 51-side diffused layer 55 and the selective gate 51, the channel below the selective gate 51 is turned into the ON-state. The held charge information is read as a current by applying potential appropriate for discriminating a threshold voltage difference in the memory gate 52 between the write and erasing states (that is, an intermediate potential between the threshold voltage in a write state and that in an erasing state).
To fabricate the memory cell shown in FIGS. 35 to 38, it is effective to form the selective gate, and then form the sidewall-shaped memory gate on a side surface of the selective gate using spacer process as disclosed in the Non-Patent Document 2. FIG. 39 is a schematic of a plane structure of a memory cell array formed by the process. FIG. 40 is a cross-sectional view taken along a line A-A of FIG. 39. If memory cells are arranged in an array, the memory array structure shown in FIG. 36 is formed. Since the spacer process is self-alignment process, there is basically no need to newly pattern the memory gate. An area of each memory cell can be, therefore, reduced. The spacer process is effective for high integration and reduction in chip area. Furthermore, a gate length of the memory gate can be made smaller than a minimum feature size, so that high current driving force can be advantageously obtained.
According to studies of the inventors of the present invention, however, the conventional method of forming the memory gate on one side surface of the selective gate using the spacer process has the following disadvantages. The conventional disadvantages will be described with reference to FIGS. 41 to 45. In each of FIGS. 41 to 45, a left part shows a cross section taken along the line A-A of FIG. 39 and a right part shows a cross section in a direction orthogonal to the line A-A.
First, as shown in FIG. 41, after the gate insulating layer 53 is formed by thermally oxidizing the substrate 50, the selective gate 51 is formed on the gate insulating layer 53 and the ONO layer 54 is formed on the substrate 50. The selective gate 51 is formed by patterning a polycrystalline silicon layer deposited on the substrate 50 by CVD (chemical vapor deposition). The ONO layer 54 is a multilayer film in which a silicon nitride layer is formed between two silicon dioxide layers, and is formed by thermal oxidation and the CVD. In FIGS. 41 to 45, reference symbol 57 denotes a device isolation trench.
As shown in FIG. 42, after a polycrystalline silicon layer is deposited on the ONO layer 54 by the CVD, the polycrystalline silicon layer is anisotropically etched, thereby forming the sidewall-shaped memory gate 52 on each of both side surfaces of the selective gate 51.
Next, as shown in FIG. 43, one of the memory gates 52 formed on the respective side surfaces of the selective gates 51 is covered with a photoresist layer 57 and the other memory gate 52 is etched and removed, thereby leaving the memory gate 52 on one surface of the selective gate 51.
After removing the photoresist layer 57, the unnecessary ONO layer 54 left on an upper surface, one side surface and the like of the selective gate 51 is etched and removed as shown in FIG. 44. At this time, it is difficult to remove the ONO layer 54 on the side surface of the selective gate 51 by dry etching. It is, therefore, necessary to remove the ONO layer 54 by wet etching with which the ONO layer 54 can be isotropically etched. If the wet etching is performed, then the ONO layer 54 is side-etched below the memory gate 52 and an end of the ONO layer 54 is retreated in a direction of the selective gate 51. A recess 59 is thereby generated below an end of the memory gate 52.
As a result, as shown in FIG. 45, when a silicon dioxide layer 60 is deposited on the substrate 50 at a later step, the silicon dioxide layer 60 cannot completely cover up an interior of the recess 59, and a cavity 61 is, therefore, formed in the silicon dioxide layer 60 near the recess 59. Furthermore, even if the cavity 61 is not formed, a density of the silicon dioxide layer 60 near the recess 59 is reduced. As a result, the silicon dioxide layer 60 near the recess 59, that is, near the end of the memory gate 52 is low in breakdown voltage.
As already stated, in the write operation performed by this memory cell, the high voltage (Vmg) is applied to the memory gate 52 and a low source voltage (Vs) is applied to the diffused layer 56, so that a strong longitudinal electric field is generated near the end of the memory gate 52. Due to this, if a low breakdown voltage region is present in the silicon dioxide layer 60 in an area of the strong longitudinal electric field, a short-circuit occurs between the memory gate 52 and the substrate 50 (diffused layer 56).
To eliminate the recess 59, there is proposed wet-etching the ONO layer 54, thermally oxidizing the substrate 50, and thereby making the ONO layer 54 below the memory gate 52 thicker. However, since a thickness of the ONO layer 54 of a nonvolatile memory in the generation of 0.13 μm to 0.18 μm is equal to or larger than 20 nanometers, it is difficult to eliminate the recess 59 by thermal oxidation.